#ifndef _NSA_HW_H
#define _NSA_HW_H

#include "nsa.h"

#define OP_REQ      0x80000000
#define OP_WRITE    0x00000000
#define OP_READ     0x40000000
#define REG_WRITE_REQ    (OP_REQ|OP_WRITE)
#define REG_READ_REQ     (OP_REQ|OP_READ)
#define REG_WAIT_REQ     OP_REQ
/* SempSec Register*/

#define SSR_VERSION  			0x10000
#define SSR_DATE				0x10004
#define SSR_BUILD				0x10008
#define SSR_MODEL				0x10010
#define SSR_INIT                0x10020

#define SSR_RESET_SEMPSEC       0x30000
#define SSR_RESET_TCAM          0x30004
#define SSR_RESET_PHY0          0x30008
#define SSR_RESET_PHY1          0x3000c
#define NSA_RESET_CMD           0x5a

#define SSR_EPLD_BUILD_LOW      0x40000
#define SSR_EPLD_BUILD_HIGH     0x40004
#define SSR_EPLD_FLASH_ADR0     0x40008
#define SSR_EPLD_FLASH_ADR1     0x4000c
#define SSR_EPLD_FLASH_ADR2     0x40010
#define SSR_EPLD_FLASH_CTRL     0x40014
#define SSR_EPLD_FLASH_DATA     0x40018
#define SSR_EPLD_DNA0           0x4001c
#define SSR_EPLD_DNA1           0x40020
#define SSR_EPLD_DNA2           0x40024
#define SSR_EPLD_DNA3           0x40028
#define SSR_EPLD_DNA4           0x4002c
#define SSR_EPLD_DNA5           0x40030
#define SSR_EPLD_DNA6           0x40034
#define SSR_EPLD_DNA7           0x40038
#define SSR_EPLD_CTRL           0x4003c
#define SSR_EPLD_STATUS         0x40040
#define SSR_EPLD_FLASH_STS      0x40044


/* don't define DIMM_A or DIMM_B, 
 * DIMM_A = SSR_DIMM_XXX+TYPE_A
 * DIMM_B = SSR_DIMM_XXX+TYPE_B
 */

#define SSR_DIMM_CTRL           0x50000
#define SSR_DIMM_MASK           0x50008
#define SSR_DIMM_DATA0          0x50100
#define SSR_DIMM_DATA_DELTA     0x00004
#define SSR_DIMM_TYPE_A         0x00000
#define SSR_DIMM_TYPE_B         0x10000
#if ((SSR_DIMM_TYPE_A != NSA_DIMM_A)||(SSR_DIMM_TYPE_B != NSA_DIMM_B))
#error "nsa_api NSA_DIMM_A/B confilct with hardware"
#endif


#define SSR_RLDRAM_CTRL         0x70000
#define SSR_RLDRAM_MASK         0x70008
#define SSR_RLDRAM_DATA0        0x70100
#define SSR_RLDRAM_DATA1        0x70104
#define SSR_RLDRAM_TYPE_A       0x00000
#define SSR_RLDRAM_TYPE_B       0x10000
#if ((SSR_RLDRAM_TYPE_A != NSA_RLDRAM_A)||(SSR_RLDRAM_TYPE_B != NSA_RLDRAM_B))
#error "nsa_api NSA_RLDRAM_A/B confilct with hardware"
#endif

#define SSR_TCAM_RESET          0x30004
#define SSR_TCAM_CTRL           0x90000
#define SSR_TCAM_INS0           0x90004
#define SSR_TCAM_INS1           0x90008
#define SSR_TCAM_INS2           0x9000c
#define SSR_TCAM_INS3           0x90010
#define SSR_TCAM_INS4           0x90014
#define SSR_TCAM_INS5           0x90018
#define SSR_TCAM_RSLT0          0x9001c
#define SSR_TCAM_RSLT1          0x90020
#define SSR_TCAM_RSLT2          0x90024
#define SSR_TCAM_RSLT3          0x90028

#define TCAM_READ_CMD           0x0
#define TCAM_WRITE_CMD          0x1
#define TCAM_LOOKUP_CMD         0x2
#define TCAM_ADT_DIRECT         0x0U
#define TCAM_ADT_INVALIDATE     0x2U
#define TCAM_ADT_FLUSH          0x4U
#define TCAM_ACT_DATA           0x0U
#define TCAM_ACT_MASK           0x1U
#define TCAM_ACT_REG            0x3U
#define TCAM_SEG_144BIT         0x3U
#define TCAM_LOOKUP_144BIT      0x5U

#if ((TCAM_ACT_DATA!=NSA_TCAM_ACT_DATA)||(TCAM_ACT_MASK!=NSA_TCAM_ACT_MASK)||(TCAM_ACT_REG !=NSA_TCAM_ACT_REG))
#error "nsa_api TCAM_ACT_DATA/MASK/REG confilct with hardware"
#endif

#define SSR_RXTX_BEGIN          0xc0000
#define SSR_MDIO_PHY0_CTRL      0xa0000
#define SSR_MDIO_PHY0_DATA      0xa0004
#define SSR_MDIO_PHY1_CTRL      0xa0010
#define SSR_MDIO_PHY1_DATA      0xa0014
#define PHY_REG_CTRL            0x0
#define PHY_REG_ID0             0x2
#define PHY_REG_SPECIFIC_CTRL   0x11
#define PHY_REG_XSPECIFIC_CTRL  0x14
#define PHY_INIT_DATA0          0x0c73
#define PHY_SRESET_CMD          0x9140


#define SSR_COUNTER_CTL         0xb0000
#define SSR_COUNTER_ADDR        0xb0004
#define SSR_COUNTER_DATAL       0xb0010
#define SSR_COUNTER_DATAH       0xb0014
#define SSR_COUNTER_CLEAR       0xb0020  /* fixme */

#define SSR_PHY_IF0             0x100000
#define SSR_PHY_IF1             0x100004
#define SSR_PHY_IF2             0x100008
#define SSR_PHY_IF3             0x10000c
#define SSR_PHY_IF4             0x100010
#define SSR_PHY_IF5             0x100014
#define SSR_PHY_IF6             0x100018
#define SSR_PHY_IF7             0x10001c
#define NSA_PHY_SPEED_10	0
#define NSA_PHY_SPEED_100	1
#define NSA_PHY_SPEED_1000	2

#define SSR_AGING_CTRL			0x140000
#define SSR_PKTUP_CTRL			0x120000

#define SSR_PKTA                NSA_SSR_ANTI_ATCK
#define SSR_PKTE                NSA_SSR_PKTE_CTRL
#define SSR_SPM_MODE            NSA_SSR_SPM_CTRL
#define SSR_SPM_CTRL            0x140010
#define SSR_SPM_ADDR            0x140014
#define SSR_SPM_DATA            0x140018
#define SSR_SPM1_DELTA          -0x010000

/*contants for hardware resources on NSA*/
// Memory size
#define SRAM_ADR_SIZE           19
#define SRAM_SIZE               (1U<<SRAM_ADR_SIZE)
#define DRAM_ADR_SIZE           25
#define DRAM_SIZE               (1U<<DRAM_ADR_SIZE)
#define TCAM_ADR_SIZE           17
#define TCAM_SIZE               (1U<<TCAM_ADR_SIZE)
#define INRAM_ADR_SIZE          20
#define INRAM_SIZE              (1U<<INRAM_ADR_SIZE)
#define EPLD_ADR_SIZE           6
#define PHY_ADR_SIZE            5

// Base of buffer is defined by SSR_FLASH_BUF_BASE
#define FLASH_BUF_SIZE          2048

// FLASH's space allocation
#define FLASH_SEMPSEC_BASE      0x0
#define FLASH_SEMPCRYPTO_BASE   0x800
    // the last block
#define FLASH_NSABC_BASE        0xfe0000


// TCAM's register address 
#define TCAM_REG_SCR            0x0
#define TCAM_REG_IDR            0x1
#define TCAM_REG_SSR0_LO        0x2
#define TCAM_REG_SSR0_UP        0x3
#define TCAM_REG_LAR_LO         0x6
#define TCAM_REG_LAR_UP         0x7

// EPLD's register address 
//#define EPLD_REG_VER            0x0
//#define EPLD_REG_BUFID          0x2
//#define EPLD_REG_FA0            0x5
//#define EPLD_REG_FA1            0x6
//#define EPLD_REG_FA2            0x7
//#define EPLD_REG_ERASE          0xb
    // new reg definition for fast flash access
#define EPLD_REG_VER            0x0
#define EPLD_REG_PCBINFO        0x1
#define EPLD_REG_ADR0           0x2
#define EPLD_REG_ADR1           0x3
#define EPLD_REG_ADR2           0x4
    // address type
#define EPLD_ADT_REG            0x1
#define EPLD_ADT_FLASH          0x0
    // Intel StrataFlash Memory command
#define FLASH_CMD_READ_ARRAY    0xff
#define FLASH_CMD_READ_STATUS   0x70
#define FLASH_CMD_ERASE         0x20
#define FLASH_CMD_ERASE_CONF    0xd0
#define FLASH_CMD_W2B           0xe8
#define FLASH_CMD_WC            0xd0


#endif /*_NSA_HW_H */
